Time-area efficient hardware architectures for cryptography and cryptanalysis

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Cryptography and cryptanalysis require efficient hardware modules, especially when attackers face budget and resource limitations. Efficient hardware implementations enhance attack speed and improve cost-performance ratios. The first part of this thesis explores hardware architectures that operate over binary finite fields in normal basis representation, relevant to applications like Elliptic Curve Cryptography. It introduces four new architectures for digit-serial normal basis multipliers and proposes a novel, compact, and scalable normal basis arithmetic unit that meets design constraints effectively. The second part delves into the cryptanalysis of the A5/1 cipher utilized in GSM communications, presenting hardware architectures for two attacks against this cipher. These represent the first documented real-world implementations of attacks against A5/1 in open literature. The attacks are executed using a low-cost special-purpose hardware device called COPACOBANA, leveraging both the cipher's properties and the capabilities of reconfigurable hardware. The design strategies outlined can be adapted for attacks on similar ciphers, showcasing their broader applicability in the field.